1. Field of the Invention
This invention relates to a silicon carbide semiconductor device such as a junction field-effect transistor (JFET). In addition, this invention relates to a method of fabricating a silicon carbide semiconductor device such as a JFET.
2. Description of the Related Art
U.S. Pat. No. 6,117,735 corresponding to Japanese patent application publication number 11-195655 discloses a method of forming a silicon carbide vertical FET in which ion implantation is implemented while a first mask and a second mask overlapping the first mask are used. As a result of the ion implantation, a first conductivity type impurity region is defined by one end of a certain portion of the first mask. The portion of the first mask and the second mask are then removed so that a second conductivity type impurity region is defined by another portion of the first mask. Thus, the first conductivity type impurity region and the second conductivity type impurity region are formed on a self-alignment basis. In the case where a mask including a tapered end portion is used and ion implantation is conducted with different accelerating-field voltages, the first conductivity type region and the second conductivity type region can be formed on a self-alignment basis using only one mask. The threshold voltage can be adjusted by controlling the impurity concentration of the channel region. The silicon carbide vertical FET is of a normally-off type.
U.S. Pat. No. 6,057,558 corresponding to Japanese patent application publication number 10-308512 discloses a trench gate type power MOSFET including a thin film of silicon carbide which defines a side of a trench. Specifically, the power MOSFET includes an n-type thin semiconductor film defining a side of the trench, and a gate oxide film occupying a bottom of the trench. The power MOSFET further includes an nxe2x88x92-type epitaxial layer and a p-type epitaxial layer between which an n+-type epitaxial layer extends. The p-type epitaxial layer, the n+-type epitaxial layer, and the nxe2x88x92-type epitaxial layer compose a pn+nxe2x88x92diode. The impurity concentration and the thickness of the n+-type epitaxial layer are chosen so that the withstand voltage of the pn+nxe2x88x92 diode will be lower than the withstand voltage of a surface of the gate oxide film in the trench bottom. As a result, the pn+nxe2x88x92 diode undergoes avalanche breakdown before the trench bottom does. Therefore, it is possible to prevent destruction of the gate oxide film.
Heinz Mitlehner et al have reported xe2x80x9cDynamic characteristics of high voltage 4H-SiC vertical JFETsxe2x80x9d, 1999 IEEE, pages 339-342. Specifically, Heinz Mitlehner et al fabricated fully implanted SiC VJFETs on n-type epilayers grown on the Si(0001)-face of n-type 4H-SiC substrates. The epilayers were grown in two steps. The first epilayer was formed. After registration masks were defined, the first epilayer was exposed to ion implantation so that the buried p-layer was implanted with aluminum. Then, the second epilayer creating the channel and pinch off region was grown onto the first epilayer. The p-gate region was implanted over the whole cell area. In three etching steps, the gate overlay, the source area and the short connection of the source region to the buried p-layer were defined. To avoid breakdown due to field crowding at the edges, a JTE-edge termination was used. After the wafers were annealed, a field oxide was deposited. Ni-contacts on back and front were defined via lithography and lift-off. After a short contact anneal, the insulation oxide was deposited and patterned via dry etching. Finally, the metallization was thermally evaporated and patterned by wet etching.
Japanese patent application publication No. 11-274173 discloses a method of fabricating a silicon carbide semiconductor device in which a mask member is formed on an nxe2x88x92-type silicon carbide epitaxial layer. Prescribed areas of the mask member are provided with openings which have inclined side surfaces. Ion implantations into the nxe2x88x92-type silicon carbide epitaxial layer via the openings are performed so that pxe2x88x92-type silicon carbide base regions and n+-type source regions are formed therein. The n+-type source regions are smaller in junction depth than the pxe2x88x92-type silicon carbide base regions. Since only one mask is used in this way, the formation of the pxe2x88x92-type silicon carbide base regions and the n+-type source regions is based on self-alignment. Therefore, the positions of the pxe2x88x92-type silicon carbide base regions and the n+-type source regions are accurate.
Japanese patent application publication number 8-288500 discloses a silicon carbide semiconductor device including a planar-type pn junction. An edge of the planar-type pn junction is of a thin flat shape to suppress concentration of electric field. The pn junction is formed by ion implantation using a mask which is made as follows. After a process of providing close adhesion between a photoresist film and a mask film is implemented, the combination of the films is exposed to isotropic etching to form the mask.
It is a first object of this invention to provide a silicon carbide semiconductor device which is excellent in on-resistance (on-state resistance), withstand voltage, and avalanche breakdown.
It is a second object of this invention to provide a method of fabricating a silicon carbide semiconductor device which is excellent in on-resistance, withstand voltage, and avalanche breakdown.
A first aspect of this invention provides a method of fabricating a silicon carbide semiconductor device. The method comprises the steps of forming a semiconductor layer (2) on a main surface of a semiconductor substrate (1), the semiconductor layer (2) and the semiconductor substrate (1) being of a first conductivity type, the semiconductor layer (2) being made of silicon carbide, the semiconductor substrate (1) being made of silicon carbide, the semiconductor layer (2) being higher in resistivity than the semiconductor substrate (1); forming a first gate region (3) in a surface portion of the semiconductor layer (2), the first gate region (3) being of a second conductivity type different from the first conductivity type; forming a channel layer (5) of the first conductivity type on the semiconductor layer (2) and the first gate region (3); forming a source region (6) of the first conductivity type in the channel layer (5), the source region (6) being opposed to the first gate region (3); forming a second gate region (7) in a surface portion of the channel layer (5), the second gate region (7) being of the second conductivity type and containing a positional range opposed to the source region (6); forming a recess (8) in the channel layer (5), the recess (8) extending through the second gate region (7) and the source region (6) and reaching the first gate region (3); forming a first gate electrode (9, 33, 42), a source electrode (9, 32, 41), and a second gate electrode (10, 32, 43), the first gate electrode (9, 33, 42) being electrically connected with the first gate region (3), the source electrode (9, 32, 41) being electrically connected with the source region (6), the second gate electrode (10, 32, 43) being electrically connected with the second gate region (7); and forming a drain electrode (12) on a back surface of the semiconductor substrate (1). The step of forming the source region (6) and the step of forming the second gate region (7) comprise the sub-steps of (a) placing first and second mask films (21, 22) on the channel layer (5), the first mask film (21) being covered with the second mask film (22); (b) forming first and second openings (21A, 22A) in the first and second mask films (21, 22) respectively; (c) implanting first ions into a first predetermined place in the channel layer (5) which is assigned to the source region (6) while using the first and second mask films (21, 22) as a mask, the first ions being first impurities corresponding to the first conductivity type; (d) implanting second ions into a second predetermined place in the channel layer (5) which is different from the first predetermined place and is assigned to a portion of the second gate region (7) while using the first and second mask films (21, 22) as a mask, the second ions being second impurities corresponding to the second conductivity type; (e) oxidating a portion of the first mask film (21) which extends from the first opening (21A) while the first mask film (21) remains covered with the second mask film (22); (f) removing the second mask film (22) and the oxidated portion of the first mask film (21); (g) implanting third ions into a third predetermined place in the channel layer (5) which is different from the first predetermined place and is assigned to the second gate region (7) while using a remaining portion (21B) of the first mask film (21) as a mask, the third ions being third impurities corresponding to the second conductivity type; and (h) activating the implanted first, second, and third impurities to form the source region (6) and the second gate region (7).
A second aspect of this invention is based on the first aspect thereof, and provides a method wherein the first mask film (21) uses a polycrystalline silicon film.
A third aspect of this invention is based on the first aspect thereof, and provides a method wherein the second mask film (22) uses one of an oxide film and a nitride film.
A fourth aspect of this invention provides a method of fabricating a silicon carbide semiconductor device. The method comprises the steps of forming a semiconductor layer (2) on a main surface of a semiconductor substrate (1), the semiconductor layer (2) and the semiconductor substrate (1) being of a first conductivity type, the semiconductor layer (2) being made of silicon carbide, the semiconductor substrate (1) being made of silicon carbide, the semiconductor layer (2) being higher in resistivity than the semiconductor substrate (1); forming a first gate region (3) in a surface portion of the semiconductor layer (2), the first gate region (3) being of a second conductivity type different from the first conductivity type; forming a channel layer (5) of the first conductivity type on the semiconductor layer (2) and the first gate region (3); forming a source region (6) of the first conductivity type in the channel layer (5), the source region (6) being opposed to the first gate region (3); forming a second gate region (7) in a surface portion of the channel layer (5), the second gate region (7) being of the second conductivity type and containing a positional range opposed to the source region (6); forming a recess (8) in the channel layer (5), the recess (8) extending through the second gate region (7) and the source region (6) and reaching the first gate region (3); forming a first gate electrode (9, 33, 42), a source electrode (9, 32, 41), and a second gate electrode (10, 32, 43), the first gate electrode (9, 33, 42) being electrically connected with the first gate region (3), the source electrode (9, 32, 41) being electrically connected with the source region (6), the second gate electrode (10, 32, 43) being electrically connected with the second gate region (7); and forming a drain electrode (12) on a back surface of the semiconductor substrate (1). The step of forming the source region (6) and the step of forming the second gate region (7) comprise the sub-steps of (a) placing a mask film (21) on the channel layer (5); (b) forming an openings (21A) in the first mask film (21); (c) after the step (b), implanting first ions into a first predetermined place in the channel layer (5) which is assigned to the source region (6) while using the mask film (21) as a mask, the first ions being first impurities corresponding to the first conductivity type; (d) after the step (b), implanting second ions into a second predetermined place in the channel layer (5) which is different from the first predetermined place and is assigned to a portion of the second gate region (7) while using the mask film (21) as a mask, the second ions being second impurities corresponding to the second conductivity type; (e) subjecting the mask film (21) to isotropic etching to expand the opening; (f) after the step (e), implanting third ions into a third predetermined place in the channel layer (5) which is different from the first predetermined place and is assigned to the second gate region (7) while using a remaining portion (21F) of the mask film (21) as a mask, the third ions being third impurities corresponding to the second conductivity type; and (g) activating the implanted first, second, and third impurities to form the source region (6) and the second gate region (7).
A fifth aspect of this invention is based on the fourth aspect thereof, and provides a method wherein the mask film (21) uses a polycrystalline silicon film.
A sixth aspect of this invention is based on the first aspect thereof, and provides a method further comprising the step of forming a body break region (4) located below the first gate region (3) and being of the first conductivity type.
A seventh aspect of this invention is based on the sixth aspect thereof, and provides a method wherein the step of forming the first gate region (3) and the step of forming the body break region (4) comprise ion implantations using a same mask.
An eighth aspect of this invention is based on the first aspect thereof, and provides a method wherein the step of forming the first gate region (3) comprises the sub-steps of implanting boron ions into the surface portion of the semiconductor layer (2), the boron ions being impurities corresponding to the second conductivity type, activating the impurities in the surface portion of the semiconductor layer (2) to form the first gate region (3), and diffusing the impurities out of the first gate region (3) to form a second-conductivity-type region (3a) deeper than the first gate region (3).
A ninth aspect of this invention is based on the first aspect thereof, and provides a method wherein one among the step of forming the first gate region (3), the step of forming the source region (6), and the step of forming the second gate region (7) comprises the sub-step of using a mixture of fourth impurities corresponding to the first conductivity type and fifth impurities corresponding to the second conductivity type.
A tenth aspect of this invention is based on the ninth aspect thereof, and provides a method wherein in cases where one among the step of forming the first gate region (3) and the step of forming the second gate region (7) comprises the sub-step of using a mixture of fourth impurities corresponding to the first conductivity type and fifth impurities corresponding to the second conductivity type, a density of the fifth impurities is higher than that of the fourth impurities; and in cases where the step of forming the source region (6) comprises the sub-step of using a mixture of fourth impurities corresponding to the first conductivity type and fifth impurities corresponding to the second conductivity type, a density of the fourth impurities is higher than that of the fifth impurities.
An eleventh aspect of this invention is based on the first aspect thereof, and provides a method wherein the step of forming the first gate region (3), the step of forming the channel layer (5), and the step of forming the second gate region (7) comprise the sub-steps of setting impurity concentrations of the first gate region (3), the channel layer (5), and the second gate region (7) so that a depletion layer extending from the first gate region (3) and a depletion layer extending from the second gate region (7) cause the channel layer (5) to be in a pinch-off state in the absence of application of a voltage to the first gate region (3) and the second gate region (7).
A twelfth aspect of this invention is based on the eleventh aspect thereof, and provides a method wherein the step of forming the channel layer (5) comprises the sub-step of setting the impurity concentration of the channel layer lower than that of the semiconductor layer (2).
A thirteenth aspect of this invention provides a silicon carbide semiconductor device comprising a semiconductor substrate (1) having a main surface and a back surface opposite to each other, the semiconductor substrate (1) being made of silicon carbide and being of a first conductivity type; a semiconductor layer (2) extending on the main surface of the semiconductor substrate (1), the semiconductor layer (2) being made of silicon carbide and being of the first conductivity type, the semiconductor layer (2) being higher in resistivity than the semiconductor substrate (1); a first gate region (3) extending in a surface portion of the semiconductor layer (2), the first gate region (3) being of a second conductivity type different from the first conductivity type; a channel layer (5) extending on the semiconductor layer (2) and the first gate region (3) and being of the first conductivity type; a source region (6) extending in the channel layer (5), the source region (6) being of the first conductivity type and being opposed to the first gate region (3); a second gate region (7) extending in a surface portion of the channel layer (5), the second gate region (7) being of the second conductivity type and containing a positional range opposed to the source region (6); a recess (8) extending in the channel layer (5), the recess (8) extending through the second gate region (7) and the source region (6) and reaching the first gate region (3); a first gate electrode (9, 33, 42) electrically connected with the first gate region (3); a source electrode (9, 32, 41) electrically connected with the source region (6); a second gate electrode (10, 32, 43) electrically connected with the second gate region (7); a drain electrode (12) extending on the back surface of the semiconductor substrate (1); and a body break region (4) located below the first gate region (3) and being of the first conductivity type, the body break region (4) having an impurity concentration higher than that of the semiconductor layer (2).
A fourteenth aspect of this invention is based on the thirteenth aspect thereof, and provides a silicon carbide semiconductor device further comprising a second-conductivity-type region (3a) adjoining an edge of the first gate region (3) and being deeper than the first gate region (3), the second-conductivity-type region (3a) having an impurity concentration lower than that of the first gate region (3).